In integrated circuits, there is generally a piece of silicon known as a die or chip which contains electrical circuits and which is connected to a lead frame. The chip has bonding pads which are connected to the lead frame by tiny wires. The lead frame has leads which are used for connecting to a printed circuit board as part of a larger system. The leads of the lead frame have a certain amount of inductance as well as capacitance and resistance. There is also some inductance in the wire from the bonding pad to the lead frame. The connection of the lead frame to a circuit board also adds some inductance. As the switching speeds of integrated circuits have increased, this cumulative inductance has begun to have an impact on the performance of the integrated circuit.
Generally, it is desirable to have integrated circuits which are very fast. The increased switching speed also increases the rate at which current changes. This increased rate of current change causes a voltage drop across the inductance. The voltage across an inductance is equal to the inductance time the time rate of change of the current through that inductance. This is expressed as LDi/dt, where L is the inductance and di/dt is the time rate of change of the current. As the di/dt becomes larger, the voltage across the inductance becomes larger. Accordingly, the voltage drop across the inductance in the wire connecting the bonding pad to the lead frame causes a voltage differential between the lead location on the circuit board and the bonding pad to which it is connected on the integrated circuit. This can create a problem of having the internal power supply at a different voltage than the voltage of the external supply.
Today's high-performance microprocessors require high speed output buffers capable of switching large capacitive loads. Typically, a CMOS output buffer uses a P-channel pull-up transistor and an N-channel pull-down transisitor, coupled to an output terminal, for providing an output signal which is a function of the data received from the other logic circuitry of the microprocessor. In the case where the output driver transistors are very fast devices, their increased switching speed increases the rate at which the current changes. The increased switching speeds of these high-performance devices increases the rate at which the current changes, thereby causing current surges on the power supply lines. The simultaneous operation of the P-channel and N-channel driver transistors, during their transition from one logic state to another, may also contribute to current surges on the power supply lines. These undesirable noise spikes on the power supply lines typically translate to output signal ringing.
One approach to solve these problems is to use additional power supply pins, thereby distributing the current surges over a greater number of pins. This approach is often impractical, due to the additional chip area required for its implementation, and the incremental packaging costs associated with high pin-count packages. Another approach is to reduce the device size in the output buffer, thereby limiting the change in current attributable to the output buffer switching. Generally, this approach adversely affects the speed and ultimately the performance of the microprocessor. Yet another approach is to anticipate the di/dt spike associated with the buffer logic state transition, and incorporate delay circuitry to compensate for the higher di/dt. This approach, disclosed in U.S. Pat. No. 4,758,743, by Dehganpour et al entitled "Output Buffer with Improved Di/Dt" is an improvement but still not optimum.